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semiconductor technical data 31 rev 6 ? motorola, inc. 1995 10/95 31 rev 1 ? motorola, inc. 1996 3/96 ! # "! ! ! highperformance silicongate cmos the mc54/74c4060a is identical in pinout to the standard cmos mc14060b. the device inputs are compatible with standard cmos out - puts; with pullup resistors, they are compatible with lsttl outputs. this device consists of 14 masterslave flipflops and an oscillator with a frequency that is controlled either by a crystal or by an rc circuit connected externally. the output of each flipflop feeds the next and the frequency at each output is half of that of the preceding one. the state of the counter advances on the negativegoing edge of the osc in. the activehigh reset is asynchronous and disables the oscillator to allow very low power consumption during standby operation. state changes of the q outputs do not occur simultaneously because of internal ripple delays. therefore, decoded output signals are subject to decoding spikes and may have to be gated with osc out 2 of the hc4060a. ? output drive capability: 10 lsttl loads ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 2 to 6 v ? low input current: 1 m a ? high noise immunity characteristic of cmos devices ? in compliance with jedec standard no. 7a requirements ? chip complexity: 390 fets or 97.5 equivalent gates logic diagram q4 7 q5 5 q6 4 q7 6 q8 14 q9 13 q10 15 q12 1 q13 2 q14 3 osc in 11 reset 12 pin 16 = v cc pin 8 = gnd osc out 1 osc out 2 9 10 15 16 14 13 12 11 10 2 1 3 4 5 6 7 v cc 9 8 q10 q8 q9 reset osc in osc out 1 osc out 2 q12 q13 q14 q6 q5 q7 q4 gnd pinout: 16lead plastic package (top view)
function table clock reset output state x l l h no charge advance to next state all outputs are low d suffix soic package case 751b05 n suffix plastic package case 64808 1 16 1 16 j suffix ceramic package case 62010 1 16 ordering information mc54hcxxxxaj mc74hcxxxxan mc74hcxxxxad mc74hcxxxxadt ceramic plastic soic tssop 1 16 dt suffix tssop package case 748c03
mc54/74hc4060a motorola highspeed cmos logic data dl129 e rev 6 32 ??????????????????????? ??????????????????????? ??????????????????????? ??????????????????????? maximum ratings* ??? ??? ??? ??? symbol ?????????????? ?????????????? ?????????????? ?????????????? parameter ?????? ?????? ?????? ?????? value ??? ??? ??? ??? unit ??? ??? ??? ??? v cc ?????????????? ?????????????? ?????????????? ?????????????? dc supply voltage (referenced to gnd) ?????? ?????? ?????? ?????? 0.5 to + 7.0 ??? ??? ??? ??? v ??? ??? ??? ??? v in ?????????????? ?????????????? ?????????????? ?????????????? dc input voltage (referenced to gnd) ?????? ?????? ?????? ?????? 0.5 to v cc + 0.5 ??? ??? ??? ??? v ??? ??? ??? ??? v out ?????????????? ?????????????? ?????????????? ?????????????? dc output voltage (referenced to gnd) ?????? ?????? ?????? ?????? 0.5 to v cc + 0.5 ??? ??? ??? ??? v ??? ??? ??? ??? i in ?????????????? ?????????????? ?????????????? ?????????????? dc input current, per pin ?????? ?????? ?????? ?????? 20 ??? ??? ??? ??? ma ??? ??? ??? ??? i out ?????????????? ?????????????? ?????????????? ?????????????? dc output current, per pin ?????? ?????? ?????? ?????? 25 ??? ??? ??? ??? ma ??? ??? ??? ??? i cc ?????????????? ?????????????? ?????????????? ?????????????? dc supply current, v cc and gnd pins ?????? ?????? ?????? ?????? 50 ??? ??? ??? ??? ma ??? ??? ??? ??? ??? p d ?????????????? ?????????????? ?????????????? ?????????????? ?????????????? power dissipation in still air, plastic or ceramic dip2 soic package2 tssop package2 ?????? ?????? ?????? ?????? ?????? 750 500 450 ??? ??? ??? ??? ??? mw ??? ??? ??? ??? t stg ?????????????? ?????????????? ?????????????? ?????????????? storage temperature range ?????? ?????? ?????? ?????? 65 to + 150 ??? ??? ??? ??? c ??? ??? ??? ??? ??? ??? t l ?????????????? ?????????????? ?????????????? ?????????????? ?????????????? ?????????????? lead t emperature, 1 mm from case for 10 seconds plastic dip, soic or tssop package ceramic dip ?????? ?????? ?????? ?????? ?????? ?????? 260 300 ??? ??? ??? ??? ??? ??? c * maximum ratings are those values beyond which damage to the device may occur . functional operation should be restricted to the recommended operating conditions. 2derating e plastic dip: 10 mw/ c from 65 to 125 c ceramic dip: 10 mw/ c from 100 to 125 c soic package: 7 mw/ c from 65 to 125 c tssop package: 6.1 mw/ c from 65 to 125 c for high frequency or heavy load considerations, see chapter 2 of the motorola highspeed cmos data book (dl129/d). recommended operating conditions ???? ???? ???? ???? symbol ?????????????? ?????????????? ?????????????? ?????????????? parameter ??? ??? ??? ??? min ??? ??? ??? ??? max ??? ??? ??? ??? unit ???? ???? ???? ???? v cc ?????????????? ?????????????? ?????????????? ?????????????? dc supply voltage (referenced to gnd) ??? ??? ??? ??? 2.5* ??? ??? ??? ??? 6.0 ??? ??? ??? ??? v ???? ???? ???? ???? v in , v out ?????????????? ?????????????? ?????????????? ?????????????? dc input voltage, output voltage (referenced to gnd) ??? ??? ??? ??? 0 ??? ??? ??? ??? v cc ??? ??? ??? ??? v ???? ???? ???? ???? t a ?????????????? ?????????????? ?????????????? ?????????????? operating temperature range, all package types ??? ??? ??? ??? 55 ??? ??? ??? ??? + 125 ??? ??? ??? ??? c ???? ???? ???? ???? ???? ???? t r , t f ?????????????? ?????????????? ?????????????? ?????????????? ?????????????? ?????????????? input rise/fall time v cc = 2.0 v (figure 1) v cc = 4.5 v v cc = 6.0 v ??? ??? ??? ??? ??? ??? 0 0 0 ??? ??? ??? ??? ??? ??? 1000 500 400 ??? ??? ??? ??? ??? ??? ns * the oscillator is guaranteed to function at 2.5 v minimum. however, parametrics are tested at 2.0 v by driving pin 11 with an external clock source. dc characteristics (voltages referenced to gnd) symbol parameter condition v cc v guaranteed limit unit symbol parameter condition v cc v 55 to 25 c 85 c 125 c unit v ih minimum highlevel input voltage v out = 0.1v or v cc 0.1v |i out | 20 m a 2.0 3.0 4.5 6.0 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 v v il maximum lowlevel input voltage v out = 0.1v or v cc 0.1v |i out | 20 m a 2.0 3.0 4.5 6.0 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 v v oh minimum highlevel output voltage (q4q10, q12q14) v in = v ih or v il |i out | 20 m a 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 v v in =v ih or v il |i out | 2.4ma |i out | 4.0ma |i out | 5.2ma 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however , precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance cir - cuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
mc54/74hc4060a highspeed cmos logic data dl129 e rev 6 33 motorola dc characteristics (voltages referenced to gnd) symbol unit guaranteed limit v cc v condition parameter symbol unit 125 c 85 c 55 to 25 c v cc v condition parameter v ol maximum lowlevel output voltage (q4q10, q12q14) v in = v ih or v il |i out | 20 m a 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v v in = v ih or v il |i out | 2.4ma |i out | 4.0ma |i out | 5.2ma 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 v oh minimum highlevel output voltage (osc out 1, osc out 2) v in = v cc or gnd |i out | 20 m a 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 v v in =v cc or gnd |i out | 0.7ma |i out | 1.0ma |i out | 1.3ma 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 v ol maximum lowlevel output voltage (osc out 1, osc out 2) v in = v cc or gnd |i out | 20 m a 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v v in =v cc or gnd |i out | 0.7ma |i out | 1.0ma |i out | 1.3ma 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 i in maximum input leakage current v in = v cc or gnd 6.0 0.1 1.0 1.0 m a i cc maximum quiescent supply current (per package) v in = v cc or gnd i out = 0 m a 6.0 4 40 160 m a note: information on typical parametric values can be found in chapter 2 of the motorola highspeed cmos data book (dl129/d). ac characteristics (c l = 50 pf, input t r = t f = 6 ns) symbol parameter v cc v guaranteed limit unit symbol parameter v cc v 55 to 25 c 85 c 125 c unit f max maximum clock frequency (50% duty cycle) (figures 1 and 4) 2.0 3.0 4.5 6.0 6.0 10 30 50 9.0 14 28 45 8.0 12 25 40 mhz t plh , t phl maximum propagation delay, osc in to q4* (figures 1 and 4) 2.0 3.0 4.5 6.0 300 180 60 51 375 200 75 64 450 250 90 75 ns t plh , t phl maximum propagation delay, osc in to q14* (figures 1 and 4) 2.0 3.0 4.5 6.0 500 350 250 200 750 450 275 220 1000 600 300 250 ns t phl maximum propagation delay, reset to any q (figures 2 and 4) 2.0 3.0 4.5 6.0 195 75 39 33 245 100 49 42 300 125 61 53 ns t plh , t phl maximum propagation delay, qn to qn+1 (figures 3 and 4) 2.0 3.0 4.5 6.0 75 60 15 13 95 75 19 16 125 95 24 20 ns
mc54/74hc4060a motorola highspeed cmos logic data dl129 e rev 6 34 ac characteristics (c l = 50 pf, input t r = t f = 6 ns) continued symbol parameter v cc v guaranteed limit unit symbol parameter v cc v 55 to 25 c 85 c 125 c unit t tlh , t thl maximum output transition time, any output (figures 1 and 4) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 16 110 36 22 19 ns c in maximum input capacitance 10 10 10 pf note: for propagation delays with loads other than 50 pf, and information on typical parametric values, see chapte r 2 o f the motorola high speed cmos data book (dl129/d). * for t a = 25 c and c l = 50 pf , typical propagation delay from clock to other q outputs may be calculated with the following equations: v cc = 2.0 v: t p = [93.7 + 59.3 (n1)] ns v cc = 4.5 v: t p = [30.25 + 14.6 (n1)] ns v cc = 3.0 v: t p = [61.5+ 34.4 (n1)] ns v cc = 6.0 v: t p = [24.4 + 12 (n1)] ns c pd power dissipation capacitance (per package)* typical @ 25 c, v cc = 5.0 v pf c pd power dissipation capacitance (per package)* 35 pf * used to determine the noload dynamic power consumption: p d = c pd v cc 2 f + i cc v cc . for load considerations, see chapter 2 of the motorola highspeed cmos data book (dl129/d). timing requirements (input t r = t f = 6 ns) symbol parameter v cc v guaranteed limit unit symbol parameter v cc v 55 to 25 c 85 c 125 c unit t rec minimum recovery time, reset inactive to clock (figure 2) 2.0 3.0 4.5 6.0 100 75 20 17 125 100 25 21 150 120 30 25 ns t w minimum pulse width, clock (figure 1) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 16 110 36 23 19 ns t w minimum pulse width, reset (figure 2) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 16 110 36 23 19 ns t r , t f maximum input rise and fall times (figure 1) 2.0 3.0 4.5 6.0 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns note: information on typical parametric values can be found in chapter 2 of the motorola highspeed cmos data book (dl129/d).
mc54/74hc4060a highspeed cmos logic data dl129 e rev 6 35 motorola pin descriptions inputs osc in (pin 11) negativeedge triggering clock input. a hightolow tran - sition on this input advances the state of the counter . osc in may be driven by an external clock source. reset (pin 12) activehigh reset. a high level applied to this input asynch - ronously resets the counter to its zero state (forcing all q out - puts low) and disables the oscillator. outputs q4eq10, q12q14 (pins 7, 5, 4, 6, 13, 15, 1, 2, 3) activehigh o utputs . e ac h q n o utpu t d ivide s t h e c lock input frequency by 2 n . the user should note the q1, q2, q3 and q11 are not available as outputs. osc out 1, osc out 2 (pins 9, 10) oscillator outputs. these pins are used in conjunction with osc in and the external components to form an oscillator (see no t ag and no t ag). when osc in is being driven with an external clock source, osc out 1 and osc out 2 must be left open circuited. with the crystal oscillator configuration in figure 6, osc out 2 must be left open circuited. switching waveforms t w t f osc in q v cc gnd 90% 50% 10% t r t w 90% 50% 10% t phl 1/f max t plh t tlh t thl reset v cc gnd t phl 50% figure 1. figure 2. q v cc gnd 50% osc in 50% t rec 50% qn v cc gnd 50% qn+1 c l * *includes all probe and jig capacitance test point device under test output figure 3. figure 4. test circuit t plh t phl
mc54/74hc4060a motorola highspeed cmos logic data dl129 e rev 6 36 figure 5. expanded logic diagram c c r osc out 2 9 q q c c r q q c c q q c c q q c c q q c c q q4 7 q5 5 q12 1 q13 2 q14 3 q6 = pin 4 q7 = pin 6 q8 = pin 14 q9 = pin 13 q10 = pin 15 v cc = pin 16 gnd = pin 8 osc out 1 10 osc in 11 reset 12 figure 6. oscillator circuit using rc configuration reset 12 osc in 11 osc out 1 10 osc out 2 9 r tc c tc r s for 2.0v v cc 6.0v 10r tc > r s > 2r tc 400hz f 400khz: f 1 3 r tc c tc (f in hz, r tc in ohms, c tc in farads) the formula may vary for other frequencies. figure 7. pierce crystal oscillator circuit reset 12 osc in 11 osc out 1 10 9 osc out 2 r f c1 c2 r1
mc54/74hc4060a highspeed cmos logic data dl129 e rev 6 37 motorola table 1. crystal oscillator amplifier specifications (t a = 25 c; input = pin 11, output = pin 10) type positive reactance (pierce) input resistance, r in 60m w minimum output impedance, z out (4.5v supply) 200 w (see text) input capacitance, c in 5pf typical output capacitance, c out 7pf typical series capacitance, c a 5pf typical open loop v oltage gain with output at full swing, a 3vdc supply 4vdc supply 5vdc supply 6vdc supply 5.0 expected minimum 4.0 expected minimum 3.3 expected minimum 3.1 expected minimum pierce crystal oscillator design figure 8. equivalent crystal networks r s l s c s re xe 2 1 2 1 2 1 c o value are supplied by crystal manufacturer (parallel resonant crystal). figure 9. series equivalent crystal load figure 10. parasitic capacitances of the amplifier z load jx co jx c2 r jx c jx cs jx ls r s r load x load note: c = c1 + c in and r = r1 + r out . c o is considered as part of the load. c a and r f typically have minimal effect below 2mhz. c in c out c a values are listed in table 1.
mc54/74hc4060a motorola highspeed cmos logic data dl129 e rev 6 38 design procedures the following procedure applies for oscillators operating below 2mhz where z is a resistor r1. above 2mhz, additional impedance elements should be considered: c out and c a of the amp, feedback resistor r f , and amplifier phase shift error from 180 c. step 1: calculate the equivalent series circuit of the crystal at the frequency of oscillation. z e jx c o (r s jx l s jx c s ) jx c o r s jx l s jx c s r e jx e reactance jx e should be positive, indicating that the crystal is operating as an inductive reactance at the oscillation frequency . the maximum r s for the crystal should be used in the equation. step 2: determine b , the attenuation, of the feedback network. for a closed-loop gain of 2,a n b = 2, b = 2/a n where a n is the gain of the hc4060a amplifier . step 3: determine the manufacturer ' s loading capacitance. for example: a manufacturer may specify an external load capaci - tance of 32pf at the required frequency . step 4: determine the required q of the system, and calculate r load , for example, a manufacturer specifies a crystal q of 100,000. in-circuit q is arbitrarily set at 20% below crystal q or 80,000. then r load = (2 p f o l s /q) r s where l s and r s are crystal parameters. step 5: simultaneously solve, using a computer , x c x c2 r r e x c2 (x e x c ) ( eq 1 ) (with feedback phase shift = 180 ) x e x c2 x c r e x c2 r x c load ( eq 2 ) (where the loading capacitor is an external load, not including c o ) r load rx c o x c2 [(x c x c2 )(x c x c o ) x c (x c x c o x c2 )] x 2 c2 (x c x c o ) 2 r 2 (x c x c o x c2 ) 2 ( eq 3 ) here r = r out + r1. r out is amp output resistance, r1 is z. the c corresponding to x c is given by c = c1 + c in . alternately, pick a value for r1 (i.e, let r1 = r s ). solve equations 1 and 2 for c1 and c2. use equation 3 and the fact that q = 2 p f o l s /(r s + r load ) to find in-circuit q. if q is not satisfactory pick another value for r1 and repeat the procedure. choosing r1 power is dissipated in the ef fective series resistance of the crystal. the drive level specified by the crystal manufacturer is the maximum stress that a crystal can withstand without damage or excessive shift in frequency . r1 limits the drive level. to verify that the maximum dc supply voltage does not overdrive the crystal, monitor the output frequency as a func - tion of voltage at osc out 2 (pin 9). the frequency should increase very slightly as the dc supply voltage is increased. an overdriven crystal will decrease in frequency or become unstable with an increase in supply voltage. the operating supply voltage must be reduced or r1 must be increased in value if the overdriven condition exists. the user should note that the oscillator start-up time is proportional to the value of r1. selecting r f the feedback resistor, r f , typically ranges up to 20m w . r f determines the gain and bandwidth of the amplifier . proper bandwidth insures oscillation at the correct frequency plus roll-off to minimize gain at undesirable frequencies, such as the first overtone. r f must be large enough so as to not af fect the phase of the feedback network in an appreciable manner . acknowledgements and recommended references the following publications were used in preparing this data sheet and are hereby acknowledged and recommended for reading: technical note tn-24, statek corp. technical note tn-7, statek corp. d. babin, adesigning crystal oscillatorso, machine design, march 7, 1985. d . b abin , a guideline s f o r c rysta l o scillato r d esigno, machine design, april 25, 1985. also recommended for reading: e. hafner , athe piezoelectric crystal unit-definitions and method of measuremento, proc. ieee, v ol. 57, no. 2, feb., 1969. d. k emper , l . r osine , a quart z c rystal s f o r f requency controlo, electro-technology, june, 1969. p. j. ottowitz, aa guide to crystal selectiono, electronic design, may, 1966.
mc54/74hc4060a highspeed cmos logic data dl129 e rev 6 39 motorola clock reset q4 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384 q5 q6 q7 q8 q9 q10 q12 q13 q14 figure 11. timing diagram
mc54/74hc4060a motorola highspeed cmos logic data dl129 e rev 6 310 outline dimensions j suffix ceramic package case 62010 issue v n suffix plastic package case 64808 issue r 19.05 6.10 e 0.39 1.40 0.21 3.18 19.93 7.49 5.08 0.50 1.65 0.38 4.31 0 0.51 15 1.01 1.27 bsc 2.54 bsc 7.62 bsc min min max max inches millimeters dim 0.750 0.240 e 0.015 0.055 0.008 0.125 0.785 0.295 0.200 0.020 0.065 0.015 0.170 0.050 bsc 0.100 bsc 0.300 bsc a b c d e f g j k l m n 0 0.020 15 0.040 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dim f may narrow to 0.76 (0.030) where the lead enters the ceramic body. 1 8 9 16 a b c k n g e f d 16 pl t seating plane m l j 16 pl 0.25 (0.010) t a m s 0.25 (0.010) t b m s min min max max inches millimeters dim a b c d f g h j k l m s 18.80 6.35 3.69 0.39 1.02 0.21 2.80 7.50 0 0.51 19.55 6.85 4.44 0.53 1.77 0.38 3.30 7.74 10 1.01 0.740 0.250 0.145 0.015 0.040 0.008 0.110 0.295 0 0.020 0.770 0.270 0.175 0.021 0.070 0.015 0.130 0.305 10 0.040 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. 2.54 bsc 1.27 bsc 0.100 bsc 0.050 bsc a b 1 8 9 16 f h g d 16 pl s c t seating plane k j m l t a 0.25 (0.010) m m 0.25 (0.010) t b a m s s min min max max millimeters inches dim a b c d f g j k m p r 9.80 3.80 1.35 0.35 0.40 0.19 0.10 0 5.80 0.25 10.00 4.00 1.75 0.49 1.25 0.25 0.25 7 6.20 0.50 0.386 0.150 0.054 0.014 0.016 0.008 0.004 0 0.229 0.010 0.393 0.157 0.068 0.019 0.049 0.009 0.009 7 0.244 0.019 1.27 bsc 0.050 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 1 8 9 16 a b d 16 pl k c g t seating plane r x 45 m j f p 8 pl 0.25 (0.010) b m m d suffix plastic soic package case 751b05 issue j
mc54/74hc4060a highspeed cmos logic data dl129 e rev 6 311 motorola outline dimensions dt suffix tssop package case 948c03 issue b a b pin 1 identification l 1 8 9 16 d c seating g h f m dim a min max min max inches 5.10 0.200 millimeters b 4.30 4.50 0.169 0.177 c 1.20 0047 d 0.05 0.25 0.002 0.010 f 0.45 0.55 0.018 0.022 g 0.65 bsc 0.026 bsc h 0.22 0.23 0.009 0.010 j 0.09 0.24 0.004 0.009 k 0.16 0.32 0.006 0.013 l 6.30 6.50 0.248 0.256 m 0 10 0 10 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimensions a and b are to be determined at datum plane u. j1 0.09 0.18 0.004 0.007 k1 0.16 0.26 0.006 0.010 k k1 j j1 section aa a a 16x ref k 0.100 (0.004) m 0.200 (0.008) m t plane p t u how to reach us: usa/europe : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, toshikatsu otsuki, p.o. box 20912; phoenix, arizona 85036. 18004412447 6f seibubutsuryucenter, 3142 tatsumi kotoku, tokyo 135, japan. 0335218315 mfax : rmf ax0@email.sps.mot.com touchtone (602) 2446609 hong kong : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, internet : http://designnet.com 51 ting kok road, tai po, n.t., hong kong. 85226629298 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages. at ypicalo parameters can and do vary in dif ferent applications. all operating parameters, including at ypicalso must be validated for each customer application by customer ' s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur . should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af firmative action employer . mc54/74hc4060a/d
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